Compare CMOS NAND and NOR gates we can see the work of the NAND gate is another series of tubes, the output voltage with the increase of the number of tubes; or non-doors on the contrary, the working tube parallel to each other, the output voltage will not have significant impact. Thus used more or door. The figure above shows the basic BiCMOS inverter circuit, for clarity, MOSFET symbol M denotes BJT with T said. T1 and T2 constitute a push-pull output stage. And Mp, MN, M1, M2 and the input stage composed of a basic CMOS inverter is very similar. VI same input signal acting on the gate of MP and MN. When vI high voltage conduction and MP MN deadline; and when vI is low voltage, the situation is the opposite, Mp conduction, MN deadline. When the output terminal of similar BiCMOS gate, the output stage can provide enough current to charge a capacitive load. Similarly, the charged capacitive load can quickly discharge through T2. After the delay time reaches, cell phone jammer will be automatically shut off.
The circuit in T1 and T2 can be stored charge in the base region through the release of M1 and M2 in order to speed up the circuit’s switching speed. When vI high voltage conduction M1, T1-base storage charge dissipating rapidly. This effect with TTL gates similar to the input level of T1.
CMOS inverter in the case of capacitive load, it’s opening time and closing time are equal, this is because the nature of the circuit with complementary symmetry. The figure indicates that when the vI = 0V when, TN deadline, TP conduction from VDD through the TP to the charging of load capacitance CL. As the CMOS inverter, the two values of gm are designed to be larger, the smaller its resistance, the charging circuit time constant smaller. Similarly, also analyzes the CL capacitor discharge process. CMOS inverter, the average transmission delay time is about 10ns. cell phone jammer intelligent management system can perform function of safety and protection.
The figure is 2 input CMOS NAND gate, which consists of two series of N-channel enhancement type MOS tube and two parallel P-channel enhancement mode MOS. Each input connected to an N-channel and a P-channel MOS gate control. When the input A, B as long as there is a low, will make the NMOS connected to it, closing, and it is connected PMOS transistor, the output is high; only when A, B are all high-power Usually, only the two series NMOS transistors are turned on, the two parallel PMOS transistors are off, the output is low. When the input A, B as long as there is a high, will make its turn connected to the NMOS, PMOS transistor connected to it, closing the output is low; only when A, B are all low Usually, two parallel NMOS transistors are off, the two series PMOS transistors are conducting, the output is high. Overview of 3g cell phone jammer intelligent system will be introduced in details.